The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Digital-to-analog converters (DACs) receive a digital input signal and convert the digital input signal into an analog output signal. The digital input signal has a range of digital codes that are converted into a continuous range of analog signal levels of the analog output signal. Accordingly, DACs are typically used to convert data between applications operating in digital and analog domains. For example only, applications of DACs include, but are not limited to, video display drivers, audio systems, digital signal processing, function generators, digital attenuators, data storage and transmission, precision instruments, and data acquisition systems.
A variety of types of DACs are available based upon desired functionality. For example only, DACs may have varying predetermined resolutions of the digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Various DAC performance factors include, but are not limited to, settling time, full scale transition time, accuracy or linearity, and resolution.
A number of bits (i.e. a bit width) of the digital input signal defines the resolution, a number of output (quantization) levels, and a total number of digital codes that are acceptable for the DAC. For example, if the digital input signal is m-bits wide, the DAC has 2m output levels.
In sub-binary radix (i.e. sub-radix2) DACs, the ratio of a weighted DAC element to a next (lower) weighted DAC element is a constant less than 2 (i.e. sub-binary). For example only, the ratio may be approximately 1.85.
Referring now to FIG. 1, an example sub-binary radix DAC 10 includes a ladder module 12 having m ladder bits and a switch control module 14. For example only, the ladder module 12 is an R-βR ladder. The ladder module 12 receives analog reference signals 16 and 18. For example only, the analog reference signal 16 may be ground and the analog reference signal 18 may be a positive reference voltage. The switch control module 14 receives bits b0, b1, . . . , bm-1 of an m-bit binary digital input signal 20 and controls switches (not shown) of the ladder module 12 based on the m bits of the digital input signal 20. The ladder module 12 generates an analog output signal 22 based on the digital input signal 20 (i.e. the controlled switches of the ladder module 12) and the analog reference signals 16 and 18. Accordingly, the analog output signal 22 corresponds to the digital-to-analog conversion of the digital input signal 20.
Referring now to FIG. 2, the ladder module 12 of the DAC 10 is shown to include resistors RL0 . . . RLm-1, referred to collectively as RLi, and resistors RDL0 . . . RDLm-1, referred to collectively as resistors RDLi. Each of the resistors RLi has a value R and each of the resistors RDLi has a value βR. In other words, β corresponds to a ratio of an RDL resistor value to an RL resistor value. A termination resistor RT has a value of γR. The values of β and γ satisfy the equation γ2=β+γ. The radix of the DAC 10 corresponds to
      γ          γ      -      1        .The analog reference signals 16 and 18 are selectively provided to the resistors RT and RDLi via switches 30.
The sub-binary radix DAC 10 is not monotonic. In other words, a transfer function of the DAC 10 is non-monotonic and a conversion between the non-monotonic transfer function and a monotonic transfer function is needed. Further, due to code overlapping, a dynamic range of the DAC 10 is reduced. Consequently, the DAC 10 uses additional bits to recover the dynamic range, and an algorithm is used to convert the bits of the m-bit binary digital input signal 20 to a sub-radix DAC code having additional bits. Conversion between the non-monotonic transfer function and the monotonic transfer function is performed via a calibration step and a radix conversion step.
The calibration step is performed using an example recursive successive approximation method. The method determines a last code having a smaller value than an analog bit weight of a current bit for each of the bits of the digital input signal 20 (from the LSB to the MSB). Results of the method are used to generate a calibration table that associates each bit i from 0 to m−1 with a corresponding digital weight WLi. An example calibration table 50 for m=4 is shown in FIG. 3. The example calibration table 50 corresponds to the following design parameters: effective number of bits (i.e. bits of input DAC code)=3; radix DAC number of bits=4; and radix=1.5.
The radix conversion step is performed using an example successive subtraction method. The method performs successive subtraction of the digital weight WLi from the binary input value of the digital input signal 20 to determine which bits of the DAC 10 are set and which bits of the DAC 10 are cleared. Results of the method are used to generate a radix DAC code, and subsequently an output value, for each input DAC code. For example only, a code mapping table 70 as shown in FIG. 4 illustrates a relationship between input DAC codes from 000 to 111 and corresponding radix DAC codes and output values. The example code mapping table 70 corresponds to the following design parameters: effective number of bits=3; radix DAC number of bits=4; and radix=1.5.